Synonyms for mdio or Related words with mdio
Examples of "mdio"
When the PHY drives the
line, the PHY has to provide the
signal between 0 and 300 ns after the rising edge of the clock. Hence, with a minimum clock period of 400 ns (2.5 MHz maximum clock rate) the MAC can safely sample
during the second half of the low cycle of the clock..
During a write command, the MAC provides address and data. For a read command, the PHY takes over the
line during the turnaround bit times, supplies the MAC with the register data requested, then releases the
The Management Data Input/Output (
) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At powerup the PHY usually adapts to whatever it is connected to (autonegotiation) unless settings are altered via the
When the MAC drives the
line, it has to guarantee a stable value 10 ns (setup time) before the rising edge of the clock MDC. Further,
has to remain stable 10 ns (hold time) after the rising edge of MDC.
There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial
/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so this must also be handled using the
/MDC interface, just like the duplex setting. Version 1.2 of the RMII Consortium specification states that its
/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 803.2 specify a standard
/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex.
This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices,
, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port.
Management Data Input/Output (
), also known as Serial Management Interface (SMI) or Media Independent Interface Management (MIIM), is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface, or MII. The MII connects Media Access Control (MAC) devices with Ethernet physical layer (PHY) circuits. The MAC device controlling the
is called the Station Management Entity (SME).
requires a specific pull-up resistor of 1.5 kΩ to 10 kΩ, taking into account the total worst-case leakage current of 32 PHYs and one MAC.
Future versions of the RMII standard might specify a way to transmit data over TXD0/TXD1/RXD0/RXD1 pins while TX_EN and CRS_DV are de-asserted. This may allow for real-time conveyance of parameters such as link speed or duplex without needing to poll the
/MDC serial link.
The interface requires 18 signals, out of which only two (
and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals. For this reason, the reduced media independent interface was developed.
Before a register access, PHY devices generally require a preamble of 32 ones to be sent by the MAC on the
line. The access consists of 16 control bits, followed by 16 data bits. The control bits consist of 2 start bits, 2 access type bits (read or write), the PHY address (5 bits), the register address (5 bits), and 2 "turnaround" bits.
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